Chiplet Collaboration: Unified Initiative Advancing Integration at the Package Scale
The TechXchange event recently provided insights into the design process of Universal Chiplet Interconnect Express (UCIe), an open standard for implementing high-bandwidth, low-latency interconnects between chiplets.
UCIe 2.0, the latest standard, boasts several new features, including the optional UCIe DFx Architecture (UDA). This vendor-agnostic management fabric connects chiplets to support improved manageability, enhancing testing, telemetry, and debugging.
Companies like Global Unichip Corp. (GUC) and Cadence have already demonstrated UCIe technology in action. GUC recently taped out UCIe physical layer (PHY) IP on TSMC’s N5 process and showcased UCIe-32G silicon on TSMC’s N3P process, targeting AI, HPC, and networking applications with high bandwidth and power efficiency using TSMC’s SoIC-X and CoWoS packaging.
Cadence, too, has showcased UCIe in practice, highlighting the open chiplet ecosystem at the package level. The company's design demonstration at TechXchange underscores the potential of UCIe for practical applications.
The UCIe Consortium, which manages the standard, emphasised that UCIe 2.0 is fully backwards compatible, ensuring seamless integration with existing systems.
The discussion at TechXchange focused on the practical aspects of designing with UCIe, providing a platform for sharing experiences and real-world examples of UCIe implementation. The event underscores the growing interest in UCIe for practical applications, with experts and companies alike recognising its potential to revolutionise the development of complex chiplet-based systems.
In a short video introduction, Brian Rea, Marketing WorkGroup Chair at the UCIe Consortium, provided a concise overview of UCIe, setting the stage for the event's discussions.
In summary, UCIe supports high-bandwidth, low-latency die-to-die interconnects, as demonstrated by companies like GUC and Cadence. The optional UCIe DFx Architecture enhances testing, telemetry, and debugging, enabling robust manageability in complex chiplet-based systems. The TechXchange event provided valuable insights into the practical applications of UCIe, underscoring its potential to transform the design and development of advanced technology systems.
Data-and-cloud-computing technologies can significantly benefit from the high-bandwidth, low-latency interconnects offered by UCIe, as demonstrated by the practical applications showcased by companies like Global Unichip Corp. (GUC) and Cadence.
The adoption of UCIe, a technology already being utilized by companies for AI, HPC, and networking applications, could revolutionize the design and development process in data-and-cloud-computing sectors.
